Circuit and Layout Techniques for Soft error resilient Digital CMOS Circuits

This book PDF is perfect for those who love Electronic Books genre, written by Hsiao-Heng Kelin Lee and published by Stanford University which was released on 07 May 2024 with total hardcover pages 156. You could read this book directly on your devices with pdf, epub and kindle format, check detail and related Circuit and Layout Techniques for Soft error resilient Digital CMOS Circuits books below.

Circuit and Layout Techniques for Soft error resilient Digital CMOS Circuits
Circuit and Layout Techniques for Soft error resilient Digital CMOS Circuits
Author : Hsiao-Heng Kelin Lee
File Size : 52,9 Mb
Publisher : Stanford University
Language : English
Release Date : 07 May 2024
ISBN : STANFORD:dn086pk6955
Pages : 156 pages
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Circuit and Layout Techniques for Soft error resilient Digital CMOS Circuits by Hsiao-Heng Kelin Lee Book PDF Summary

Radiation-induced soft errors are a major concern for modern digital circuits, especially memory elements. Unlike large Random Access Memories that can be protected using error-correcting codes and bit interleaving, soft error protection of sequential elements, i.e. latches and flip-flops, is challenging. Traditional techniques for designing soft-error-resilient sequential elements generally address single node errors, or Single Event Upsets (SEUs). However, with technology scaling, the charge deposited by a single particle strike can be simultaneously collected and shared by multiple circuit nodes, resulting in Single Event Multiple Upsets (SEMUs). In this work, we target SEMUs by presenting a design framework for soft-error-resilient sequential cell design with an overview of existing circuit and layout techniques for soft error mitigation, and introducing a new soft error resilience layout design principle called LEAP, or Layout Design through Error-Aware Transistor Positioning. We then discuss our application of LEAP to the SEU-immune Dual Interlocked Storage Cell (DICE) by implementing a new sequential element layout called LEAP-DICE, retaining the original DICE circuit topology. We compare the soft error performance of SEU-immune flip-flops with the LEAP-DICE flip-flop using a test chip in 180nm CMOS under 200-MeV proton radiation and conclude that 1) our LEAP-DICE flip-flop encounters on average 2,000X and 5X fewer errors compared to a conventional D flip-flop and our reference DICE flip-flop, respectively; 2) our LEAP-DICE flip-flop has the best soft error performance among all existing SEU-immune flip-flops; 3) In the evaluation of our design framework, we also discovered new soft error effects related to operating conditions such as voltage scaling, clock frequency setting and radiation dose.

Circuit and Layout Techniques for Soft error resilient Digital CMOS Circuits

Circuit and Layout Techniques for Soft error resilient Digital CMOS Circuits by Hsiao-Heng Kelin Lee

Radiation-induced soft errors are a major concern for modern digital circuits, especially memory elements. Unlike large Random Access Memories that can be protected using error-correcting codes and bit interleaving, soft error protection of sequential elements, i.e. latches and flip-flops, is challenging. Traditional techniques for designing soft-error-resilient sequential elements generally

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Circuit and Layout Techniques for Soft error resilient Digital CMOS Circuits

Circuit and Layout Techniques for Soft error resilient Digital CMOS Circuits by Hsiao-Heng Kelin Lee

Radiation-induced soft errors are a major concern for modern digital circuits, especially memory elements. Unlike large Random Access Memories that can be protected using error-correcting codes and bit interleaving, soft error protection of sequential elements, i.e. latches and flip-flops, is challenging. Traditional techniques for designing soft-error-resilient sequential elements generally

Get Book
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